This is a NOR/OR gate using emitter-coupled logic, a high-speed type of logic using transistors. The two inputs are shown at left. If either one of them is high (-700 mV), then the OR output is high, and the NOR output is low. If they are both low (-1.4V), then the OR is low, and NOR is high.

Q3's base voltage is fixed at a level where there is enough base current to get Q3 to conduct. This brings Q3's collector down to about 740 mV, which brings the OR output low (through a follower attached to Q3's collector). Q3's emitter is high enough relative to Q2's base that Q2 can't conduct, so Q2's collector stays at ground. This keeps the NOR output high (through a follower).

If either of the two inputs is high, then the corresponding transistor conducts. This brings Q1/Q2's collector low, which brings the NOR output low. It also brings Q1/Q2's emitter high enough so that Q3 can't conduct, which brings the OR output high.

The advantage of ECL is speed, because the transistors are never in saturation. They are either in cutoff or forward-active mode; transistors can switch between these two states quickly. The disadvantage is that there is always a lot of current, and therefore power consumption.

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Generated Wed Dec 7 2016